The present invention relates to a video signal conversion method and more particularly to the video signal conversion method for displaying a video signal having an aspect ratio of 4:3 on a screen having an aspect ratio of 16:9.
The screen aspect ratio that gives one the feeling of being at a live performance is 16:9. However, the aspect ratio of most screens used in general-purpose televisions is 4:3. A television having a screen aspect ratio of 16:9, for example, a wide screen television, has been used, thus giving the viewer a feeling of being at a live performance.
FIG. 1 shows a video signal having an aspect ratio of 4:3 (hereinafter referred to as a "4:3 video signal") displayed on a screen having an aspect ratio of 16:9 (hereinafter referred to as a "16:9 screen") so that the viewer can feel as if present at a live performance. FIG. 1A shows the 4:3 video signal displayed at the center of the 16:9 screen (hereinafter referred to as a "center mode"), and FIG. 1B shows the 4:3 video signal displayed on the left side of the 16:9 screen (hereinafter referred to as a "pop mode"). Displaying the 4:3 video signal on the 16:9 screen without any processing causes the original 4:3 video signal to be displayed with dispersion and out of focus (i.e., with dissimilation). In order to display the 4:3 video signal on the 16:9 screen without such dissimilation occurring, some methods have been suggested and used. One such method is to decimate the original 4:3 video signal by a factor of 3/4 (i.e., 3/4 decimation).
FIG. 2 is a diagram for describing a conventional video signal conversion method for 3/4 decimating the original 4:3 video signal and displaying the decimated signal on the 16:9 screen.
An input data signal is synchronized with a write clock W.sub.CLK and stored in a memory 20. The data stored in memory 20 is synchronized with a read clock R.sub.CLK and then output. Read clock R.sub.CLK has a frequency 4/3 that of write clock W.sub.CLK. Since the data being output is generated by 3/4 decimating the original 4:3 signal, it can be displayed on the 16:9 screen without dissimilation occurring.
However, in the case of converting the 4:3 video signal, as described above, since read clock R.sub.CLK and write clock W.sub.CLK have different frequencies, separate phase locked loops for read clock R.sub.CLK and write clock W.sub.CLK are respectively required. In addition, if read clock R.sub.CLK and write clock W.sub.CLK having different frequencies, are used, high frequency interference noise occurs between read clock R.sub.CLK and write clock W.sub.CLK, between read clock R.sub.CLK and the video signal, or between write clock W.sub.CLK and the video signal.